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INTEGRATED CIRCUITS
74LVT573 3.3 V Octal D-type transparent latch (3-State)
Product data Supersedes data of 1998 Feb 19 File under Integrated Circuits, IC23 Handbook 2001 Dec 17
Philips Semiconductors
Philips Semiconductors
Product data
3.3 V Octal D-type transparent latch (3-State)
74LVT573
FEATURES
* Inputs and outputs on opposite side of package allow easy
interface to microprocessors
DESCRIPTION
The LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled independently by Enable (E) and Output Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors. The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition. The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance "OFF" state, which means they will neither drive nor load the bus.
* 3-State output buffers * Common output enable * TTL input and output switching levels * Input and output interface capability to systems at 5 V supply * Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
* Live insertion/extraction permitted * No bus current loading when output is tied to 5 V bus * Latch-up protection exceeds 500 mA per JEDEC Std 17 * Power-up 3-State * Power-up reset * ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ PARAMETER Propagation delay Dn to Qn Input capacitance Output capacitance Total supply current CONDITIONS Tamb = 25 C; GND = 0 V CL = 50 pF; VCC = 3.3 V VI = 0 V or 3.0 V Outputs disabled; VO = 0 V or 3.0 V Outputs disabled; VCC = 3.6 V TYPICAL 2.5 2.7 4 8 0.13 UNIT ns pF pF mA
ORDERING INFORMATION
PACKAGES 20-Pin Plastic SOL 20-Pin Plastic SSOP Type II 20-Pin Plastic TSSOP Type I TEMPERATURE RANGE -40 C to +85 C -40 C to +85 C -40 C to +85 C TYPE NUMBER 74LVT573D 74LVT573DB 74LVT573PW DWG NUMBER SOT163-1 SOT339-1 SOT360-1
PIN CONFIGURATION
OE D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 E
PIN DESCRIPTION
PIN NUMBER 1 2, 3, 4, 5, 6, 7, 8, 9 19, 18, 17, 16, 15, 14, 13, 12 11 10 20 SYMBOL OE D0-D7 Q0-Q7 E GND VCC FUNCTION Output enable input (active-Low) Data inputs Data outputs Enable input (active-High) Ground (0 V) Positive supply voltage
GND 10
SV00031
2001 Dec 17
2
853-1750 27467
Philips Semiconductors
Product data
3.3 V Octal D-type transparent latch (3-State)
74LVT573
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
1 11
EN C1
2
3
4
5
6
7
8
9
D0 11 E
D1
D2 D3
D4
D5
D6
D7
2 3 4
1D
19 18 17 16 15 14 13 12
1
OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
5 6 7
19
18
17
16
15
14
13
12 8
SV00032
9
SV00033
FUNCTION TABLE
INPUTS OE L L L L L H= h= L= l= NC= X= Z= = E H H L Dn L H I h X INTERNAL REGISTER L H L H NC OUTPUTS Q0 - Q7 L H L H NC Z OPERATING MODE
Enable and read register Latch and read register Hold Disable outputs
H X X NC High voltage level High voltage level one set-up time prior to the High-to-Low E transition Low voltage level Low voltage level one set-up time prior to the High-to-Low E transition No change Don't care High impedance "off" state High-to-Low E transition
LOGIC DIAGRAM
D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9
D
D
D
D
D
D
D
D
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
11 E 1 OE 19 Q0 18 Q1 17 Q2 16 Q3 15 Q4 14 Q5 13 Q6 12 Q7
SV00034
2001 Dec 17
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Philips Semiconductors
Product data
3.3 V Octal D-type transparent latch (3-State)
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IO OUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 DC output current Output in High state Storage temperature range -64 -65 to 150 VO < 0 Output in Off or High state Output in Low state VI < 0 CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to +7.0 -50 -0.5 to +7.0 128
74LVT573
UNIT V mA V mA V mA C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IO OL t/v Tamb DC supply voltage Input voltage High-level input voltage Input voltage High-level output current Low-level output current Low-level output current; current duty cycle 50%, f 1kHz Input transition rise or fall rate; outputs enabled Operating free-air temperature range -40 PARAMETER MIN 2.7 0 2.0 0.8 -32 32 mA 64 10 +85 ns/V C MAX 3.6 5.5 V V V V mA UNIT
2001 Dec 17
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Philips Semiconductors
Product data
3.3 V Octal D-type transparent latch (3-State)
74LVT573
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40 C to +85 C MIN VIK Input clamp voltage VCC = 2.7 V; IIK = -18 mA VCC = 2.7 V to 3.6 V; IOH = -100 A VOH High-level output voltage VCC = 2.7 V; IOH = -8 mA VCC = 3.0 V; IOH = -32 mA VCC = 2.7 V; IOL = 100 A VCC = 2.7 V; IOL = 24 mA VOL Low-level output voltage VCC = 3.0 V; IOL = 16 mA VCC = 3.0 V; IOL = 32 mA VCC = 3.0 V; IOL = 64 mA VRST Power-up output low voltage5 VCC = 3.6 V; IO = 1 mA; VI = GND or VCC VCC = 0 or 3.6 V; VI = 5.5 V II Input l k I t leakage current t VCC = 3.6 V; VI = VCC or GND VCC = 3.6 V; VI = VCC VCC = 3.6 V; VI = 0 V IOFF IHOLD Output off current Bus Hold current A inputs7 Current into an output in the High state when VO > VCC Power-up/down 3-State output current3 3-State output High current 3-State output Low current VCC = 0 V; VI or VO = 0 V to 4.5 V VCC = 3 V; VI = 0.8 V VCC = 3 V; VI = 2.0 V VCC = 0 V to 3.6 V; VCC = 3.6 V IEX IPU/PD IOZH IOZL ICCH ICCL ICCZ ICC Additional supply current per input pin2 Quiescent supply current VO = 5.5 V; VCC = 3.0 V VCC 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC; OE/OE = Don't care VCC= 3.6 V; VO = 3 V; VI = VIL or VIH VCC= 3.6 V; VO = 0.5 V; VI = VIL or VIH VCC = 3.6 V; Outputs High, VI = GND or VCC, IO = 0 VCC = 3.6 V; Outputs Low, VI = GND or VCC, IO = 0 VCC = 3.6 V; Outputs Disabled; VI = GND or VCC, IO = 05 VCC = 3 V to 3.6 V; One input at VCC-0.6 V, Other inputs at VCC or GND 75 -75 500 60 1 1 -1 0.13 3 0.13 0.1 125 100 5 -5 0.19 12 0.19 0.2 mA mA A A A Control pins Data pins4 VCC-0.2 2.4 2.0 TYP1 -0.9 VCC-0.1 2.5 2.2 0.1 0.3 0.25 0.3 0.4 0.13 1 0.1 0.1 -1 1 150 -150 A 0.2 0.5 0.4 0.5 0.55 0.55 10 1 1 -5 100 A A A V V V MAX -1.2 V UNIT
NOTES: 1. All typical values are at VCC = 3.3 V and Tamb = 25 C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND. 3. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 msec. From VCC = 1.2 V to VCC = 3.3 V 0.3 V a transition time of 100 sec is permitted. This parameter is valid for Tamb = 25 C only. 4. Unused pins at VCC or GND. 5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 6. ICCZ is measured with outputs pulled to VCC or GND. 7. This is the bus hold overdrive current required to force the input to the opposite logic state.
2001 Dec 17
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Philips Semiconductors
Product data
3.3 V Octal D-type transparent latch (3-State)
74LVT573
AC CHARACTERISTICS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 ; Tamb = -40 C to +85 C. LIMITS SYMBOL tPLH tPHL tPLH tPHL tPZH tPZL PARAMETER Propagation delay Dn to Qn Propagation delay E to Qn Output enable time to High and Low level WAVEFORM MIN 2 1 4 5 4 5 1.0 1.0 1.6 2.5 1.0 1.3 2.0 1.5 VCC = 3.3 V 0.3 V TYP1 2.5 2.7 3.5 4.3 2.8 3.3 3.7 3.0 MAX 4.2 4.3 5.6 6.5 5.1 5.5 5.7 4.6 VCC = 2.7 V MAX 4.7 5.2 6.3 7.2 6.2 6.6 6.7 5.1 ns ns ns ns UNIT
tPHZ Output disable time from High and Low level tPLZ NOTE: 1. All typical values are at VCC = 3.3 V and Tamb = 25 C.
AC SETUP REQUIREMENTS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 ; Tamb = -40 C to +85 C. LIMITS SYMBOL tS(H) tS(L) th(H) th(L) tw(H) PARAMETER WAVEFORM VCC = 3.3 V 0.3 V MIN Set-up time, High or Low, Dn to E Hold time, High or Low, Dn to E E pulse width High 3 3 1 0.7 0.7 1.6 1.6 3.3 MAX VCC = 2.7 V MIN 0.6 0.6 1.8 1.8 3.3 ns ns ns UNIT
AC WAVEFORMS
VM = 1.5 V, VIN = GND to 2.7 V
2.7V
E
1.5V tw(H) tPHL
1.5V
1.5V 0V tPLH VOH
Dn
Qn
1.5V
1.5V VOL
E
SV00035
Waveform 1. Propagation Delay, Enable to Output, and Enable Pulse Width
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
SV00118
2.7V
Dn
1.5V
1.5V 0V
tPLH
tPHL VOH
Qn
1.5V
1.5V VOL
SV00117
Waveform 2. Propagation Delay for Data to Outputs
2001 Dec 17
6
EEEEEEEEE EEE E EEEEEEEEE EEE E EEEEEEEEE EEE E
1.5V 1.5V 1.5V 1.5V ts(H) th(H) ts(L) th(L) 1.5V 1.5V
2.7V
0V
2.7V
0V
Waveform 3. Data Set-up and Hold Times
Philips Semiconductors
Product data
3.3 V Octal D-type transparent latch (3-State)
74LVT573
2.7V 2.7V
OE
1.5V
1.5V 0V
OE
1.5V
1.5V 0V
tPZH
tPHZ VOH tPZL tPLZ VOH -0.3V 0V
3V
Qn
1.5V
Qn
1.5V
VOL +0.3V VOL
SV00119
SV00120
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
TEST CIRCUIT AND WAVEFORM
VCC 6.0 V Open VIN PULSE GENERATOR RT D.U.T. VOUT RL GND tW VM 10% tTHL (tF) tTLH (tR) 10% 0V CL RL tTLH (tR) tTHL (tF) 90% VM 10% tW 0V AMP (V) VM AMP (V)
90% NEGATIVE PULSE
90%
Test Circuit for 3-State Outputs
90% POSITIVE PULSE 10% VM
SWITCH POSITION
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH SWITCH Open 6V GND
VM = 1.5 V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74LVT 2.7 V Rep. Rate v10 MHz tW tR tF
500 ns v2.5 ns v2.5 ns
SV00092
2001 Dec 17
7
Philips Semiconductors
Product data
3.3 V Octal D-type transparent latch (3-State)
74LVT573
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
2001 Dec 17
8
Philips Semiconductors
Product data
3.3 V Octal D-type transparent latch (3-State)
74LVT573
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
2001 Dec 17
9
Philips Semiconductors
Product data
3.3 V Octal D-type transparent latch (3-State)
74LVT573
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
2001 Dec 17
10
Philips Semiconductors
Product data
3.3 V Octal D-type transparent latch (3-State)
74LVT573
NOTES
2001 Dec 17
11
Philips Semiconductors
Product data
3.3 V Octal D-type transparent latch (3-State)
74LVT573
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2001 All rights reserved. Printed in U.S.A. Date of release: 12-01
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 09251
Philips Semiconductors
2001 Dec 17 12

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